The power consumption of electronic systems has increased considerably. This is the result, on the one hand, of the increase in the computing power necessary to perform complex tasks and, on the other hand, of the ever-growing volume of data to be processed. Indeed, when an electronic system processes a large volume of data, activity on the interconnections increases, and this has the effect of significantly increasing the power consumption of the electronic system. In this respect, studies show that, in current chip systems, the interconnections represent up to 60% of the total power consumption of the chip.
Numerous research works relate to the optimization of the power consumption of interconnections, especially by introducing encoders-decoders into electronic systems.
For example, the so-called “partial bus invert” technique, described in the document entitled Partial bus invert coding for power optimization of system level bus; Y. Shin, S. I K Chae and K. Choi; In processing of the 1998 international symposium on low power electronics and design (ISLPED); on pages 127-129 New York USA, 1998 ACM Press, consists in comparing the number of bits changing between a datum n−1 at clock cycle t−1 and a datum n at clock cycle t. If this difference, which is generally called the Hamming distance, is greater than half the width of the bus, then the datum sent at clock cycle t will be the complemented datum.
Nevertheless, the establishment of these techniques requires the addition of extra transistors, registers and electrical wires, which involves a new increase in the electrical energy consumed, so that the cost premium in terms of power consumption generated by these electronic components is sometimes equivalent to or even greater than the saving in power consumption obtained on the interconnection.